Title:
【発明の名称】相互接続部テストユニットを有する回路及び第1電子回路と第2電子回路との間の相互接続部をテストする方法
Document Type and Number:
Japanese Patent JP2001520780
Kind Code:
A
Abstract:
An electronic circuit comprises a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects. A main unit implements a normal mode function of the electronic circuit. A test unit tests the interconnects. The electronic circuit has a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit. In the test mode the test unit is operable as a low complexity memory via the I/O nodes.
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Inventors:
Dijon Franciscus Heme
Murris Macias N
Ray McAlls Robertas M
Louthberg Guillaume Air
Murris Macias N
Ray McAlls Robertas M
Louthberg Guillaume Air
Application Number:
JP53911399A
Publication Date:
October 30, 2001
Filing Date:
January 29, 1999
Export Citation:
Assignee:
Konin Krekka Philips Electronics NV
International Classes:
G01R31/28; G01R31/3185; G06F11/22; G11C29/32; (IPC1-7): G06F11/22; G01R31/28; G06F11/22
Attorney, Agent or Firm:
Akihide Sugimura (2 outside)