Title:
【発明の名称】ディスプレイドライバ回路のピーク電流および帯域幅要件を低減する内部行シーケンサ
Document Type and Number:
Japanese Patent JP2001523845
Kind Code:
A
Abstract:
A display driver circuit includes a word line sequencer for providing a series of row addresses, and a row decoder for decoding each of the row addresses and asserting write signals on corresponding ones of a plurality of output terminals. An optional data path sequencer provides a series of path addresses which are used by an optional data router to route data to particular sub-rows of a display. Additionally, an optional sub-row sequencer provides a series of sub-row addresses to an optional sub-row decoder, which decodes each of the sub-row addresses and asserts write signals on corresponding ones of a second plurality of output terminals.
Inventors:
Pinkham, Raymond
Wally, W. Spencer, The Third
Hudson, Edwin Lyle
Campbell, John Gray
Wally, W. Spencer, The Third
Hudson, Edwin Lyle
Campbell, John Gray
Application Number:
JP2000521504A
Publication Date:
November 27, 2001
Filing Date:
November 13, 1998
Export Citation:
Assignee:
Aurora Systems, Inc.
International Classes:
G09G3/20; G09G3/36; (IPC1-7): G09G3/20
Attorney, Agent or Firm:
Shusaku Yamamoto