Title:
【発明の名称】寄生キャパシタンスを低減したキャパシタを含む電圧ブースト回路
Document Type and Number:
Japanese Patent JP2002510855
Kind Code:
A
Abstract:
A capacitor structure for an integrated circuit, the structure including a main capacitor and a parasitic capacitor, comprising: a substrate 2000 of a first conductivity type; a first dielectric layer 2040; a first conductive layer 2010 disposed over the first dielectric layer 2040, said first conductive layer 2010 forming a first plate of the main capacitor and a first plate of the parasitic capacitor; a second dielectric layer 2020 disposed over the first conductive layer 2010; and a second conductive layer 2030 disposed over the second dielectric layer 2020, the second conductive layer 2030 forming a second plate of the main capacitor; characterized in that the capacitor structure further comprises a well 2100 disposed within the substrate 2000 which is of a second conductivity type opposite to said first type, the first dielectric layer 2040 is disposed over the well 2100 and the well 2100 forms a second plate of the parasitic capacitor and a further, junction capacitor with the substrate 2000, the configuration being such that the parasitic and junction capacitors are mutually in series and in series with the main capacitor such as to reduce stray capacitance.
Inventors:
Yelan Maanfeld
Application Number:
JP2000541698A
Publication Date:
April 09, 2002
Filing Date:
March 30, 1999
Export Citation:
Assignee:
ASTRAZENECA AKTIEBOLAG
International Classes:
H01L27/04; H01L21/02; H01L21/822; H01L29/94; H02M3/07; (IPC1-7): H01L27/04; H01L21/822; H02M3/07
Attorney, Agent or Firm:
Aoyama Ryo (1 person outside)