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Patent Searching and Data


Title:
【発明の名称】力率補正用途
Document Type and Number:
Japanese Patent JP2002544754
Kind Code:
A
Abstract:
Commercially available transition mode ("TM") power factor correction ("PFC") pre-regulator integrated circuits ("IC") typically have an output pin that is used to control a MOSFET in the power output circuit as well as a multiplier input pin that is used to set the peak current that is conducted by the MOSFET on a cycle-by-cycle basis. A portion of the rectified line voltage typically is applied to the multiplier input pin. Zero crossing distortion in the input line current is significantly decreased by reducing the range of the portion of rectified line voltage applied to the multiplier input of the TM PFC IC. The range may be reduced in any convenient manner. For example, one technique adds a clamping device such as a Zener diode to the voltage divider used to sense the rectified line voltage, so that the peak value at the PFC IC multiplier input is clamped if the rectified line voltage exceeds a certain value. Another technique actively changes the value of impedance in the voltage divider used to sense the rectified line voltage based on, for example, either the peak or average rectified line voltage. The change in the divider impedance may be achieved in any convenient manner, as for example by using a small signal transistor to switch a resistor in and out of the divider and a peak detector or average sense circuit to turn the signal transistor ON or OFF as a function of the rectified line voltage.

Inventors:
Bernd Klauberg
Rick Liang
Application Number:
JP2000617542A
Publication Date:
December 24, 2002
Filing Date:
April 27, 2000
Export Citation:
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Assignee:
Konin Krekka Philips Electronics NV
International Classes:
H02M7/12; H02M1/00; H02M1/42; (IPC1-7): H02M7/12
Attorney, Agent or Firm:
Sugimura Kosaku (1 person outside)