Title:
【発明の名称】エミュレーション・システムにおけるクロック生成及び分配
Document Type and Number:
Japanese Patent JP2003501710
Kind Code:
A
Abstract:
A method and apparatus for clock generation and distribution in an emulation system is described. The present invention provides a method and apparatus for generating a derived clock signal with a circuit having a look up table. A counter circuit counts clock cycles and provides an index into the look up table. A frequency divider circuit may be used between the counter circuit and a base clock signal to provide an intermediate clock signal with a frequency that is less than the frequency of the base clock signal. In one embodiment, a selection circuit is provided to select between the base clock signal and an external clock signal.
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Inventors:
François, Duegi
Lebrsky, Frederick
Barbieres, Jean
Lebrsky, Frederick
Barbieres, Jean
Application Number:
JP2001500405A
Publication Date:
January 14, 2003
Filing Date:
February 08, 2000
Export Citation:
Assignee:
Mentor Graphics Corporation
International Classes:
G06F1/04; G06F1/08; G06F1/10; H03K5/135; G06F11/22; (IPC1-7): G06F1/08; G06F1/04; G06F1/10; G06F11/22
Attorney, Agent or Firm:
Tadahiko Ito