Title:
【発明の名称】電界効果トランジスタ(FET)およびFET回路
Document Type and Number:
Japanese Patent JP2003514382
Kind Code:
A
Abstract:
A polymer-based or silicon-based accumulation type, depletion mode field effect transistor, suitable as a driver for load. Optionally, the load is another accumulation type, depletion mode field effect transistor. The transistor may be of the TFT type, either lateral or vertical. Optionally, it may have Schottky diode contacts to source and drain electrodes, possibly with a reverse biased Schottky junction, or it may have a negatively charged gate dielectric.
Inventors:
Eccleston, William
Lloyd, Gilles Christian Rohm
Lloyd, Gilles Christian Rohm
Application Number:
JP2001537137A
Publication Date:
April 15, 2003
Filing Date:
November 09, 2000
Export Citation:
Assignee:
The University of Liverpool
International Classes:
H01L27/088; H01L21/8234; H01L21/8238; H01L27/092; H01L29/772; H01L29/786; H01L51/05; H01L27/28; (IPC1-7): H01L29/786; H01L21/8234; H01L21/8238; H01L27/088; H01L27/092; H01L51/00
Domestic Patent References:
| JPH07176743A | 1995-07-14 | |||
| JPS62274775A | 1987-11-28 | |||
| JPH05152560A | 1993-06-18 | |||
| JPH0629537A | 1994-02-04 | |||
| JPH06310711A | 1994-11-04 |
Foreign References:
| WO1999054936A1 | 1999-10-28 |
Attorney, Agent or Firm:
Kazuo Shamoto (5 outside)