Title:
【発明の名称】パワーアップ状態用のトライステート回路
Document Type and Number:
Japanese Patent JP2003533903
Kind Code:
A
Abstract:
In an electronic circuit and/or component, such as a television, that requires a tri-state condition when the electronic circuit/component is powered up, a tri-state circuit may be employed. The present tri-state circuit includes a control circuit operably coupled to an enable input of a tristate buffer. During power-up of the electronic circuit, the control circuitry is operable to prevent data from passing from an input of the tri-state buffer to an output of the tri-state buffer until a predetermined time period wherein the control circuitry is operable to allow data to pass from the input to the output of the tri-state buffer.
Inventors:
Veil, Yehuim
Application Number:
JP2001510991A
Publication Date:
November 11, 2003
Filing Date:
July 14, 2000
Export Citation:
Assignee:
Thomson Licensing Society Anonymous
International Classes:
H03K19/0175; H03K17/22; H03K19/082; H03K19/094; (IPC1-7): H03K19/0175
Domestic Patent References:
| JPH10188560A | 1998-07-21 | |||
| JPH05315921A | 1993-11-26 | |||
| JPH05184066A | 1993-07-23 | |||
| JP2000278110A | 2000-10-06 | |||
| JPH0675668A | 1994-03-18 | |||
| JPS54158843A | 1979-12-15 |
Attorney, Agent or Firm:
Katsunori Watanabe