Title:
GPS信号を獲得するために組み合わされた並列および順次検出
Document Type and Number:
Japanese Patent JP2004502175
Kind Code:
A
Abstract:
A two part signal acquisition process includes a parallel signal detection process and signal verification/false alarm rejection process. A massively parallel architecture of acquisition correlators search a large region of the time-frequency uncertainty during the parallel signal detection process to identify the most likely detections for each search dwell. Concurrent with the parallel signal detection process performed by the acquisition correlators, the current list of most likely detections is examined with additional search dwells in the verification/false alarm rejection process. The verification/false alarm rejection process is performed by a plurality of independent correlators or tracking channels. Under software control, the tracking channels perform repeated dwells on the most likely detections until they can be dismissed as false alarms or verified as the desired signal.
Inventors:
Charles Pee Norman
Stephen, F. Rounds
Stephen, F. Rounds
Application Number:
JP2002506124A
Publication Date:
January 22, 2004
Filing Date:
June 20, 2001
Export Citation:
Assignee:
SIRF TECHNOLOGY,INC.
International Classes:
G01S1/00; G01S19/30; G01S19/37; H04B1/707; H04B1/7077; H04B1/709; (IPC1-7): G01S5/14; H04J13/04
Domestic Patent References:
| JPH06235762A | 1994-08-23 |
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki