強誘電性メモリ回路及びその製造方法

Japanese Patent JP2004515055

A

A ferroelectric memory circuit (C) comprises a ferroelectric memory cell in the form of a ferroelectric polymer thin film (F) and first and second electrodes (E1; E2) respectively, contacting the ferroelectric memory cell (F) at opposite surfaces thereof, whereby a polarization state of the cell can be set, switched or detected by applying appropriate voltages to the electrodes (E1; E2). At least one of the electrodes (E1; E2) comprises at least one contact layer (P1; P2), said at least one contact layer (P1; P2) comprising a conducting polymer contacting the memory cell (C), and optionally a second layer (M1; M2) of a metal film contacting the conducting polymer (P1; P2), whereby said at least one of the electrodes (E1; E2) either comprises a conducting polymer contact layer (P1; P2) only, or a combination of a conducting polymer contact layer (P1; P2) and a metal film layer (M1; M2). A method in the fabrication of a ferroelectric memory circuit of this kind comprises steps for depositing a first contact layer of conducting polymer thin film on the substrate, depositing subsequently a ferroelectric polymer thin film on the first contact layer, and then depositing a second contact layer on the top of the ferroelectric polymer thin film.

Johansson, Niclas
Chen, Richun

JP2002544725A

May 20, 2004

November 27, 2001

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Thin film electronics

G11C11/22; G11C13/02; H01L21/312; H01L21/8246; H01L27/105; H01L27/115; H01L27/12; H01L27/28; H01L21/02; H01L51/00; H01L51/30; (IPC1-7): H01L27/105; H01L21/312

JPH02158173A	1990-06-18
JPH03126275A	1991-05-29
JPH0764107A	1995-03-10
JP2001291842A	2001-10-19
JPH05232516A	1993-09-10
JPS6320883A	1988-01-28
JPS60257581A	1985-12-19
JPS62198176A	1987-09-01
JPS63104386A	1988-05-09

Hideto Asamura
Hajime Asamura
Katsunori Ando
Yukihiro Ikeda

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