Title:
デュアルダマシン金属配線用最適化ライナー
Document Type and Number:
Japanese Patent JP2004518291
Kind Code:
A
Abstract:
A method of forming diffusion barrier stacks on a dielectric for a dual damascene metal chip-level interconnect, and a diffusion barrier stack produced thereby. Alternating layers of a metal and an electrically resistive diffusion barrier are deposited on a dielectric substrate, with different layers having different thicknesses appropriate to their functions in the device. In an example of the present invention, alternating layers of tantalum and tantalum nitride are deposited on a dielectric substrate.
Inventors:
Hillman, Joseph, Tee
Licata, Thomas, Jay
Licata, Thomas, Jay
Application Number:
JP2002560176A
Publication Date:
June 17, 2004
Filing Date:
October 31, 2001
Export Citation:
Assignee:
東京エレクトロン株式会社
トーキョー エレクトロン アリゾナ インコーポレイテッド
トーキョー エレクトロン アリゾナ インコーポレイテッド
International Classes:
H01L21/3205; H01L21/768; H01L23/52; H01L21/28; H01L23/532; (IPC1-7): H01L21/768; H01L21/28; H01L21/3205
Attorney, Agent or Firm:
Hideto Asamura
Hajime Asamura
Katsunori Ando
Yukihiro Ikeda
Hajime Asamura
Katsunori Ando
Yukihiro Ikeda