Title:
電力増幅器のための電流ミラー補償システム
Document Type and Number:
Japanese Patent JP2004521540
Kind Code:
A
Abstract:
Two compensating resistors in a mirror bias circuit coupled to a radio frequency (RF) amplifier are configured such that transistor base-emitter voltages are adjusted to stabilize RF transistor quiescent current for variations in collector voltage, Vcc. For example, when battery power is drained during device use, Vcc decreases. As Vcc decreases, less current is drawn through the compensating resistors, thereby decreasing the voltage drop across the compensating resistors and increasing the transistor base-emitter voltages in the mirror bias circuit and the radio frequency (RF) amplifier. Thus, the tendency of the RF transistor quiescent current to decrease as Vcc decreases is off-set because the compensating resistors cause an increase in the RF transistor base-emitter voltage, thereby increasing quiescent current. In one embodiment, the first compensating resistor size is equal to the second compensating resistor size multiplied by the ratio of the buffer transistor current rating to the mirror transistor current rating.
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Inventors:
Fowler, Thomas
Application Number:
JP2002561365A
Publication Date:
July 15, 2004
Filing Date:
December 18, 2001
Export Citation:
Assignee:
Conexant Systems, Inc.
International Classes:
H03F1/30; H03F3/24; (IPC1-7): H03F1/30; H03F3/24
Attorney, Agent or Firm:
Hidekazu Miyoshi
Yasuo Miyoshi
Yasuo Miyoshi