Title:
ヒューズアレイのヒューズの抵抗を測定する方法
Document Type and Number:
Japanese Patent JP2004526164
Kind Code:
A
Abstract:
In a method of measuring fuse resistance in a fuse array, the P-MOS switches used for row address are replaced by a pass-gate device comprising an N-MOS in parallel with a P-MOS, with a close to zero voltage drop. By this means a reduced power source current is applied across the fuse. The voltage drop is measured and the resistance obtained. Thus non-destructive testing is carried out as compared to destructive testing with the prior art method.
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Inventors:
Erie, Gee Cooley
Application Number:
JP2002588211A
Publication Date:
August 26, 2004
Filing Date:
May 02, 2002
Export Citation:
Assignee:
Koninklijke Philips Electronics N.V.
International Classes:
G01R27/02; G01R31/74; G11C29/50; H01L21/82; H01L21/822; H01L27/04; (IPC1-7): G01R27/02; H01L21/82; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki