Title:
多位相符号化プロトコル及びバスの同期化
Document Type and Number:
Japanese Patent JP2004531150
Kind Code:
A
Abstract:
A multiphase encoded protocol has sufficient density of commands to allow a rich language to be realized on a bus. When ten field bits are dedicated to commands, it is possible to have more than six million words to choose from per clock. Architecture to implement the multiphase encoded protocol and synchronize the bus includes an extracted clock, a command element, and a data element. One-bit multipliers are used as correlation elements to provide feedback into slaved delay-locked loop (DLL) devices, which provides precise phase alignment for successful data extraction of several channels.
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Inventors:
Moritz, Karl
Levy, Paul
Levy, Paul
Application Number:
JP2003505784A
Publication Date:
October 07, 2004
Filing Date:
June 13, 2002
Export Citation:
Assignee:
Intel Corporation
International Classes:
H04L7/08; G06F13/42; (IPC1-7): H04L7/08
Attorney, Agent or Firm:
Tadahiko Ito
Shinsuke Onuki
Tadashige Ito
Naoki Fujimura
Shinsuke Onuki
Tadashige Ito
Naoki Fujimura