Title:
ダイのアンチヒューズによるルート指定
Document Type and Number:
Japanese Patent JP2004535661
Kind Code:
A
Abstract:
A semiconductor die is provided with an internally programmable router to assign signal paths to select connection points. A switching matrix incorporating at least one antifuse is utilized to selectively route signal paths on the semiconductor die. The chips can then be used individually, for example to reconfigure chip pin assignments to operate in a plurality of different socket layouts, or where features or controls of a chip are selectively enabled or disabled. A further alternative involves programming a first chip, then stacking piggyback, or one on top of the other, the first chip onto a second chip. The contact pins are electrically coupled together, thus avoiding the need for external frames and pin rerouting schemes to form stacked chips. In the stacked chip configuration, control pins are rerouted to align with unused pins on the chip stacked against.
Inventors:
Deuceman, Kevin
Application Number:
JP2002574230A
Publication Date:
November 25, 2004
Filing Date:
March 15, 2002
Export Citation:
Assignee:
MICRON TECHNOLOGY INCORPORATED
International Classes:
G11C5/06; G11C11/401; G11C29/48; H01L21/82; H01L23/525; H03K19/177; (IPC1-7): H01L21/82; G11C11/401; H03K19/177
Attorney, Agent or Firm:
Kazuo Shamoto
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Hideo Tanaka
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Hideo Tanaka