Title:
オーバーレイヤーパターンを使用してウェハに担持された半導体デバイスの電流制御を提供すること
Document Type and Number:
Japanese Patent JP2005500690
Kind Code:
A
Abstract:
Disclosed are methods for providing wafer parasitic current control to a semiconductor wafer (1500) having a substrate (1520), at least one active layer (1565) and a surface layer (1510), and electrical contacts (1515) formed on said surface layer (1510). Current control can be achieved with the formation of trenches (1525) around electrical contacts, where electrical contacts and associated layers define an electronic device. Insulating implants (1530) can be placed into trenches (1525) and/or sacrificial layers (1540) can be formed between electronic contacts (1515). Trenches control current by promoting current flow within active (e.g., conductive) regions (1560) and impeding current flow through inactive (e.g., nonconductive) regions (1550). Methods of and systems for wafer level burn-in (WLBI) of semiconductor devices are also disclosed. Current control at the wafer level is important when using WLBI methods and systems.
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Inventors:
Haji-Shake, Michael Jay
Beard, James Earl
Hawkins, Robert M
James Kay, Nguyenter
Beard, James Earl
Hawkins, Robert M
James Kay, Nguyenter
Application Number:
JP2003522161A
Publication Date:
January 06, 2005
Filing Date:
August 12, 2002
Export Citation:
Assignee:
Honeywell International Inc.
International Classes:
H01L21/66; G01R31/27; G01R31/28; H01S5/042; H01S5/183; H01S5/42; (IPC1-7): H01L21/66
Attorney, Agent or Firm:
Kazuo Shamoto
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Shigeo Takeuchi
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Shigeo Takeuchi