Title:
反射マスクを使用した集積回路
Document Type and Number:
Japanese Patent JP2005527964
Kind Code:
A
Abstract:
A desired pattern is formed in a photoresist layer that overlies a semiconductor wafer using a reflective mask. This mask is formed by consecutively depositing a reflective layer, an absorber layer and an anti-reflective (ARC) layer. The ARC layer is patterned according to the desired pattern. The ARC layer is inspected to find areas in which the desired pattern is not achieved. The ARC layer is then repaired to achieve the desired pattern with the absorber layer protecting the reflective layer. The desired pattern is transferred to the absorber layer to reveal the reflective portion of mask. Radiation is reflected off the reflective mask to the semiconductor wafer to expose the photoresist layer overlying the semiconductor wafer with the desired pattern.
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Inventors:
Han, Sun-In
Mangato, Pawitter
Wasson, James Earl.
Hector, Scott Di.
Mangato, Pawitter
Wasson, James Earl.
Hector, Scott Di.
Application Number:
JP2003523291A
Publication Date:
September 15, 2005
Filing Date:
August 02, 2002
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
G21K1/06; G03F1/24; G03F1/84; H01L21/027; (IPC1-7): H01L21/027; G03F1/14; G03F1/16; G21K1/06
Attorney, Agent or Firm:
Mamoru Kuwagaki