Title:
集積キャパシタンス構造を備える半導体素子、ならびにその製造方法
Document Type and Number:
Japanese Patent JP2005528784
Kind Code:
A
Abstract:
A semiconductor component has an insulating layer which is formed on a semiconductor substrate and in which a capacitance structure (K) is formed. The capacitance structure (K) has at least two metallization planes (1 to 7) which are arranged parallel to one another and are each connected to an electrical connecting line. Arranged between the metallization planes (1 to 7) is at least one electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) for producing a capacitance surface, the electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) being electrically connected only to one of the metallization planes (1 to 7).
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Inventors:
Benetic, thomas
Ruderer, Erwin
Ruderer, Erwin
Application Number:
JP2003586937A
Publication Date:
September 22, 2005
Filing Date:
March 24, 2003
Export Citation:
Assignee:
Infineon Technologies AG
International Classes:
H01L27/04; H01L21/822; H01L23/522; (IPC1-7): H01L21/822; H01L27/04
Attorney, Agent or Firm:
Kenzo Hara
Ryuichi Kijima
Ichiro Kaneko
Ryuichi Kijima
Ichiro Kaneko