Title:
SOIデバイスにおけるドープ領域の形成方法
Document Type and Number:
Japanese Patent JP2005536037
Kind Code:
A
Abstract:
In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, forming a doped region in the bulk substrate under the active layer, forming a plurality of transistors above the SOI substrate in an area above the doped region and applying a voltage to the doped region to vary a threshold voltage of at least one of the plurality of transistors. In another illustrative embodiment, the method comprises providing a consumer product comprised of at least one integrated circuit product, the integrated circuit product being comprised of a plurality of transistors formed in an active layer of an SOI substrate above a doped region formed in a bulk substrate of the SOI substrate, the doped region being formed under the active layer, sensing an activity level of the integrated circuit product and applying a voltage of a magnitude and a polarity to the doped region, the magnitude and polarity of the applied voltage being determined based upon the sensed activity level of the integrated circuit product.
Inventors:
Derrick Jay. Listers
Andy C. Way
Marc Bee. Fuse Liar
Andy C. Way
Marc Bee. Fuse Liar
Application Number:
JP2004512202A
Publication Date:
November 24, 2005
Filing Date:
May 28, 2003
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INCORPORATED
International Classes:
H01L21/8234; H01L21/8238; H01L21/84; H01L27/088; H01L27/092; H01L27/12; H01L27/08; H01L29/786; (IPC1-7): H01L27/08; H01L21/8234; H01L21/8238; H01L27/088; H01L27/092; H01L29/786
Domestic Patent References:
| JPH1041511A | 1998-02-13 | |||
| JP2000243967A | 2000-09-08 | |||
| JP2000260991A | 2000-09-22 | |||
| JPH09223802A | 1997-08-26 | |||
| JPH09162417A | 1997-06-20 | |||
| JP2001284596A | 2001-10-12 |
Foreign References:
| WO1999027585A1 | 1999-06-03 |
Attorney, Agent or Firm:
Masatake Suzuki
Ryota Sano
Yoshito Muramatsu
Ryota Sano
Yoshito Muramatsu