Title:
サーマルバジェットを低減する接合およびケイ化物の形成
Document Type and Number:
Japanese Patent JP2006526893
Kind Code:
A
Abstract:
Method of formation of a metal-silicide layer ( 12, 13, 14, 18, 19 ) an a semiconductor substrate ( 1 ), the semiconductor substrate ( 1 ) including at least a dopant region ( 5 ); the dopant region ( 5 ) including an ultra-shallow junction region; the method including as a first step at least one impurity implantation process (IB dopant) for forming the dopant region ( 5 ); the method including as a second step at least one metal implantation process (IB metal) for forming the metal-silicide layer ( 12, 13, 18, 19 ) an the dopant region ( 5 ), and the method including, as a third step carried out after the first and the second step, a low-temperature annealing process wherein simultaneously the dopant region ( 5 ) is activated and the metal-silicide layer ( 12, 13, 14, 18, 19 ) is formed.
Inventors:
Bartholomie, Jay Pouraku
Application Number:
JP2006508444A
Publication Date:
November 24, 2006
Filing Date:
May 19, 2004
Export Citation:
Assignee:
Koninklijke Philips Electronics N.V.
INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW
INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW
International Classes:
H01L21/28; H01L21/265; H01L21/285; H01L21/336; H01L29/78; H01L29/786
Domestic Patent References:
| JPH09121055A | 1997-05-06 | |||
| JPH04357828A | 1992-12-10 | |||
| JP2001237422A | 2001-08-31 | |||
| JPH0817761A | 1996-01-19 | |||
| JPH02170528A | 1990-07-02 | |||
| JP2002141504A | 2002-05-17 | |||
| JPH08125182A | 1996-05-17 |
Foreign References:
| US6534402B1 | 2003-03-18 |
Attorney, Agent or Firm:
Kenji Yoshitake
Masami Tamama
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Masami Tamama
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki