Title:
素子間分離のための半導体構造中の素子間のボイドの使用
Document Type and Number:
Japanese Patent JP2007501531
Kind Code:
A
Abstract:
A flash EEPROM or other type of memory cell array having adjacent charge storage elements is formed with a gas filled void between them in order to reduce the level of capacitive coupling between storage elements, thus reducing cross-coupling between charge storage elements and resulting errors occurring in the data read from the array.
Inventors:
Chen, Jiang
Higashiya Masaaki
Higashiya Masaaki
Application Number:
JP2006532783A
Publication Date:
January 25, 2007
Filing Date:
May 03, 2004
Export Citation:
Assignee:
SanDisk Corporation
International Classes:
H01L21/8247; H01L21/768; H01L27/115; H01L29/788; H01L29/792; H01L23/522
Attorney, Agent or Firm:
Toshi Inoguchi