Title:
電流検知方式に基づく差動回路のためのフェールセーフ
Document Type and Number:
Japanese Patent JP2007512624
Kind Code:
A
Abstract:
A system and method are described for receiving differential currents in a current mode circuit. When conditions occur where the receiver inputs are floating, undriven, shorted together, or one or both shorted to ground, the output of the system remains stable. Diode connected MOS transistors receive the unequal currents, and current mirrors amplify the received currents. Those amplified mirrored currents are differentially amplified and converted into voltage signals suitable of typical computer and logic systems. The current mode differential nature of the invention provides high common mode current and voltage noise immunity. A threshold for the unequal currents helps provide high differential current and voltage noise immunity.
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Inventors:
Pradohan, Pravas
Ju, Jiang Hong
Ju, Jiang Hong
Application Number:
JP2006541230A
Publication Date:
May 17, 2007
Filing Date:
November 08, 2004
Export Citation:
Assignee:
Fairchild Semiconductor Corporation
International Classes:
G06F11/00; G01R19/00; G01R31/02
Domestic Patent References:
| JPH0843472A | 1996-02-16 | |||
| JP2002118456A | 2002-04-19 | |||
| JP2001103098A | 2001-04-13 |
Attorney, Agent or Firm:
Satoshi Furuya
Takahiko Mizobe
Kiyoharu Nishiyama
Takahiko Mizobe
Kiyoharu Nishiyama