Title:
適応送信プリエンファシス、反射相殺、およびオフセット相殺を用いる高速シグナリングシステム
Document Type and Number:
Japanese Patent JP2007515130
Kind Code:
A
Abstract:
In a data-precessing receiver, a sampling circuit generates a plurality of samples of an incoming signal and stores the plurality of samples one after another in a first storage buffer. A first subset of the plurality of samples are transferred from the first storage buffer to a decoder circuit in response to each assertion of a first control signal, and a second subset of the plurality of samples are transferred from the first storage buffer to a tap weight update circuit in response to each assertion of a second control signal, the second strobe signal being asserted asynchronously with respect to the first control signal. The tap weight update circuit generates a plurality of updated tap weights based, at least in part, on the second subset of the plurality of samples.
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Inventors:
Stoyanovich, Vladimir, M.
Ho, Andrew
Bessios, Anthony
Chen, Fred, F.
Arad, Erado
Horowitz, Mark, A.
Gallep, Bruno, W.
Ho, Andrew
Bessios, Anthony
Chen, Fred, F.
Arad, Erado
Horowitz, Mark, A.
Gallep, Bruno, W.
Application Number:
JP2006545411A
Publication Date:
June 07, 2007
Filing Date:
December 16, 2004
Export Citation:
Assignee:
Rambus Incorporated
International Classes:
H04B3/04; H03K19/003; H04L25/02; H04L25/03; H04L25/06; H04L25/49
Attorney, Agent or Firm:
Yoshiyuki Inaba
Shinji Oga
Toshifumi Onuki
Shinji Oga
Toshifumi Onuki