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Title:
ポリマーメモリ装置の金属窒化物電極及び金属酸化物電極内への電子トラップ生成
Document Type and Number:
Japanese Patent JP2007531329
Kind Code:
A
Abstract:
An embodiment of the invention reduces damage caused to a polymer ferroelectric layer in a polymer ferroelectric memory device by creating excess holes in the insulating metal nitride and/or metal oxide layers between the metal electrodes and polymer ferroelectric layer. The excess holes in the metal nitride and/or metal oxide trap electrons injected by the metal electrodes under AC bias that would otherwise damage the polymer ferroelectric layer.

Inventors:
Lenavical, Mukuru, Pea
Oscars Dottier, Gudbyorg, H
Application Number:
JP2007506563A
Publication Date:
November 01, 2007
Filing Date:
March 31, 2005
Export Citation:
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Assignee:
Intel Corporation
International Classes:
H01L27/28; G11C11/22; G11C13/02; H01L21/00; H01L21/8246; H01L27/10; H01L27/105; H01L51/05; H01L51/30
Domestic Patent References:
JP2005519463A2005-06-30
JP2005510078A2005-04-14
JP2007531265A2007-11-01
JPH1022470A1998-01-23
JP2006510193A2006-03-23
JP2004076108A2004-03-11
JP2002026282A2002-01-25
JP2005519463A2005-06-30
JP2005510078A2005-04-14
JP2007531265A2007-11-01
JPH1022470A1998-01-23
JP2006510193A2006-03-23
JP2004076108A2004-03-11
JP2002026282A2002-01-25
Foreign References:
WO2003075279A12003-09-12
WO2003044801A12003-05-30
WO2003107351A12003-12-24
WO2003075279A12003-09-12
WO2003044801A12003-05-30
WO2003107351A12003-12-24
Attorney, Agent or Firm:
Tadahiko Ito
Shinsuke Onuki
Tadashige Ito
Koichi Sugiyama