Title:
極薄シリコンにおけるNROM型フラッシュメモリデバイス
Document Type and Number:
Japanese Patent JP2007534161
Kind Code:
A
Abstract:
An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top.
Inventors:
Forbes, Leonard
Application Number:
JP2006541306A
Publication Date:
November 22, 2007
Filing Date:
November 16, 2004
Export Citation:
Assignee:
Micron Technology, Inc.
International Classes:
H01L21/8247; H01L21/28; H01L27/10; H01L27/115; H01L29/51; H01L29/788; H01L29/792; H01L29/92
Domestic Patent References:
| JP2007508695A | 2007-04-05 | |||
| JP2003218242A | 2003-07-31 | |||
| JP2003142610A | 2003-05-16 | |||
| JPH08335643A | 1996-12-17 | |||
| JP2001326289A | 2001-11-22 | |||
| JP2003078043A | 2003-03-14 |
Foreign References:
| WO2002015277A2 | 2002-02-21 | |||
| WO2003063250A1 | 2003-07-31 | |||
| US6597037B1 | 2003-07-22 | |||
| US20020195649A1 | 2002-12-26 | |||
| WO2002065522A1 | 2002-08-22 |
Attorney, Agent or Firm:
Takehiro Chiba
Toshiyuki Miyadera
Toshiyuki Miyadera