Title:
マイクロプロセッサにおける偽エラーを低減する方法及び装置
Document Type and Number:
Japanese Patent JP2008501191
Kind Code:
A
Abstract:
A technique to reduce false error detection in microprocessors. A pi bit is propagated with an instruction through an instruction flow path. When a parity error is detected, the pi bit is set, instead of raising a machine check exception. Upon reaching a commit point, the processor can determine if the instruction was on a wrong path.
Inventors:
Mukherjee, Shubuhendu
Emer, Joel
Stephen Reinhard
Weaver, christopher
Smith, michael
Emer, Joel
Stephen Reinhard
Weaver, christopher
Smith, michael
Application Number:
JP2007515202A
Publication Date:
January 17, 2008
Filing Date:
May 20, 2005
Export Citation:
Assignee:
Intel Corporation
International Classes:
G06F9/38; G06F11/10; G06F11/14
Attorney, Agent or Firm:
Tadahiko Ito
Shinsuke Onuki
Tadashige Ito
Shinsuke Onuki
Tadashige Ito