Title:
競合しないロック命令の投機実行のための方法及び装置
Document Type and Number:
Japanese Patent JP2008504603
Kind Code:
A
Abstract:
A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will actually be contended. If not, then the lock instruction may be treated as having a normal load micro-operation which may be speculatively executed. Monitor logic may look for indications that the lock instruction is actually contended. If no such indications are found, the speculative load micro-operation and other micro-operations corresponding to the lock instruction may retire. However, if such indications are in fact found, the lock instruction may be restarted, and the prediction mechanism may be updated.
Inventors:
Saha, Blatin
Marten, matthew, sea
Hummerland, Par
Marten, matthew, sea
Hummerland, Par
Application Number:
JP2007518188A
Publication Date:
February 14, 2008
Filing Date:
June 17, 2005
Export Citation:
Assignee:
Intel Corporation
International Classes:
G06F9/38
Domestic Patent References:
| JPS626366A | 1987-01-13 | |||
| JP2002007371A | 2002-01-11 |
Foreign References:
| US20020046334A1 | 2002-04-18 | |||
| WO2001077820A2 | 2001-10-18 |
Attorney, Agent or Firm:
Tadahiko Ito
Shinsuke Onuki
Tadashige Ito
Shinsuke Onuki
Tadashige Ito