Title:
デジタルデータインタフェースデバイス
Document Type and Number:
Japanese Patent JP2008522493
Kind Code:
A
Abstract:
A cycle redundancy check, CRC, generator system (454) within a host system as well as a corresponding method is described. The system/method provides a mechanism to intentionally corrupt a CRC value. Thereby, the system (454) comprises a CRC generator (910) that generates a CRC value based on data to be included in a data packet to be transmitted over a digital transmission link, a CRC corrupter (920) that corrupts a CRC value generated by the CRC generator to convey host or related system status information, an error detector (930) that detects an error condition within a host system and provides instructions for the CRC corrupter to intentionally corrupt a CRC value. Also a corresponding CRC checker and method are described that can interpret intentionally corrupted CRC values.
Inventors:
Catibian, Burnham
Willey, George A.
Steel, Bryan
Willey, George A.
Steel, Bryan
Application Number:
JP2007543422A
Publication Date:
June 26, 2008
Filing Date:
November 23, 2005
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
H04M1/00
Domestic Patent References:
| JP2004531916A | 2004-10-14 | |||
| JP2004021613A | 2004-01-22 | |||
| JP2001282714A | 2001-10-12 | |||
| JP2002062990A | 2002-02-28 | |||
| JP2001333130A | 2001-11-30 | |||
| JP2001319745A | 2001-11-16 |
Attorney, Agent or Firm:
Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Katsu Sunagawa
Ryo Hashimoto
Tetsuya Kazama
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Katsu Sunagawa
Ryo Hashimoto
Tetsuya Kazama