Title:
最適化されたJTAGインターフェイス
Document Type and Number:
Japanese Patent JP2008538236
Kind Code:
A
Abstract:
An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.
Inventors:
Wet cell, ready.
Application Number:
JP2008503082A
Publication Date:
October 16, 2008
Filing Date:
March 21, 2006
Export Citation:
Assignee:
Texas Instruments Incorporated
International Classes:
G01R31/28; G06F1/10; G06F11/22; H01L21/822; H01L27/04
Domestic Patent References:
| JPH01217274A | 1989-08-30 | |||
| JPH10115668A | 1998-05-06 | |||
| JP2002368114A | 2002-12-20 | |||
| JP2002277514A | 2002-09-25 | |||
| JPH1194916A | 1999-04-09 | |||
| JPH1083354A | 1998-03-31 | |||
| JP2003162456A | 2003-06-06 | |||
| JP2001296334A | 2001-10-26 | |||
| JPH08204682A | 1996-08-09 | |||
| JPH04160378A | 1992-06-03 |
Attorney, Agent or Firm:
Hideto Asamura
Hajime Asamura
Hayashi Zouzo
Kuniaki Shimizu
Hajime Asamura
Hayashi Zouzo
Kuniaki Shimizu