Title:
ポリシリコン電極を有する半導体デバイス
Document Type and Number:
Japanese Patent JP2008544517
Kind Code:
A
Abstract:
A method of manufacturing a semiconductor device such as a MOS transistor. The device comprises a polysilicon gate (10) and doped regions (22,24) formed in a semiconductor substrate (12), separated by a channel region (26). The exposed surface of the semiconductor substrate is amorphized, by ion bombardment for example, so as to inhibit subsequent diffusion of the dopant ions during thermal annealing. Low thermal budgets are favored for the activation and polysilicon regrowth to ensure an abrupt doping profile for the source/drain regions. As a consequence an upper portion (10b) of the gate electrode remains amorphous. The upper portion of the gate electrode is removed so as to allow a low resistance contact to be made with the polysilicon lower portion (10a).
Inventors:
Bartolomey Yaw Paw Rack
Application Number:
JP2008516483A
Publication Date:
December 04, 2008
Filing Date:
June 13, 2006
Export Citation:
Assignee:
NXP B.V.
International Classes:
H01L29/78; H01L21/20; H01L21/28; H01L29/423; H01L29/49
Domestic Patent References:
| JPH0923007A | 1997-01-21 | |||
| JP2003022984A | 2003-01-24 | |||
| JPH0458524A | 1992-02-25 | |||
| JPH07263684A | 1995-10-13 | |||
| JPH03297148A | 1991-12-27 | |||
| JP2000260728A | 2000-09-22 | |||
| JP2003332565A | 2003-11-21 |
Attorney, Agent or Firm:
Kenji Sugimura
Kosaku Sugimura
Kiyoshi Kuruma
Shiro Fujitani
Tatsuya Sawada
Groundwork Kenichi
Kosaku Sugimura
Kiyoshi Kuruma
Shiro Fujitani
Tatsuya Sawada
Groundwork Kenichi