スタックド・レジスタ・ファイルのレジスタ・セーブ・エンジンのためのバッキング記憶装置バッファ

Title:

スタックド・レジスタ・ファイルのレジスタ・セーブ・エンジンのためのバッキング記憶装置バッファ

Document Type and Number:

Japanese Patent JP2009512941

Kind Code:

A

Abstract:

A Backing Store Buffer is interposed between a Physical Register File and the Backing Store in a stacked register file architecture. A Register Save Engine temporarily stores data from registers in the Physical Register File allocated to inactive procedures on-chip, freeing the registers to be re-allocated to new procedures. When the a procedures complete and returns control to a prior, inactive procedure, the Register Store Engine retrieves data associated with the inactive procedure from the Backing Store Buffer to registers in the Physical Register File, and the registers are re-allocated to the inactive procedure. The Register Save Engine saves data from the Backing Store Buffer to the Backing Store, incurring the significant performance degradation and power consumption required for off-chip RAM access, only when the Backing Store Buffer is full and more data must be saved from the Physical Register File.

Inventors:

Rishirik, Bohus Love

Application Number:

JP2008536645A

Publication Date:

March 26, 2009

Filing Date:

October 20, 2006

Export Citation:

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Assignee:

QUALCOMM INCORPORATED

International Classes:

G06F9/48

Domestic Patent References:

JPH02148223A

1990-06-07

Attorney, Agent or Firm:

Takehiko Suzue
Kurata Masatoshi
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Katsumura Hiro
Ryo Hashimoto
Tetsuya Kazama
Shoji Kawai
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Takuzo Ichihara
Yamashita Gen

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