Title:
内蔵メモリ内のビット線プリチャージ
Document Type and Number:
Japanese Patent JP2009528650
Kind Code:
A
Abstract:
An integrated circuit device includes a first latch having a first input to receive a first predecode value, a second input to receive a first clock signal, and an output to provide a latched first predecode value responsive to an edge event of the first clock signal. The integrated circuit device further includes a memory component. The memory component includes an input to receive the latched first predecode value and the latched second predecode value, a first bit line, and a plurality of word lines coupled to the first bit line. Each word line is associated with a corresponding bit of the latched second predecode value. The integrated circuit device further includes logic having an input to receive the corresponding bit of the latched first predecode value. The logic is to precharge the first bit line directly responsive to only a value at the corresponding bit of the latched first predecode value.
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Inventors:
Ramalaj, Ravindra Raj
Application Number:
JP2008556495A
Publication Date:
August 06, 2009
Filing Date:
February 08, 2007
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
G11C11/41; G11C11/413
Domestic Patent References:
| JPH05210983A | 1993-08-20 | |||
| JP2003151280A | 2003-05-23 | |||
| JPH1186555A | 1999-03-30 |
Foreign References:
| WO2000026920A1 | 2000-05-11 |
Attorney, Agent or Firm:
Shinjiro Ono
Kazuo Shamoto
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Shogo Nakamura
Kazuo Shamoto
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Shogo Nakamura