Title:
プラズマ処理システムのマスクアンダーカットおよびノッチを最小化する方法
Document Type and Number:
Japanese Patent JP2009539267
Kind Code:
A
Abstract:
A method for etching silicon layer of a substrate, which is deposited on a bottom electrode in a plasma processing chamber. The method includes performing a main etch step until at least 70 percent of silicon layer is etched. The method further includes an overetch step, which includes a first, second, and third process steps. The first process step employs a first process recipe, the second process step employs a second process recipe, and the third process step employs a third process recipe. The second process recipe employs a second bottom bias voltage level applied to the bottom electrode which is higher than the first bottom bias voltage level employs in the first process recipe and the third bottom bias voltage level employs in the third process recipe. The first, second, and third process steps are alternated a plurality of times until silicon layer is etched through.
Inventors:
Pandum Sophorn, Tamarak
Coffer, alfeld
Bosh, william
Coffer, alfeld
Bosh, william
Application Number:
JP2009513426A
Publication Date:
November 12, 2009
Filing Date:
May 29, 2007
Export Citation:
Assignee:
LAM RESEARCH CORPORATION
International Classes:
H01L21/3065
Domestic Patent References:
| JP2006080504A | 2006-03-23 | |||
| JP2002170814A | 2002-06-14 |
Foreign References:
| WO2005045904A2 | 2005-05-19 |
Attorney, Agent or Firm:
Hiroe Associates Patent Office