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Title:
ステッチされるICチップ・レイアウトの方法、システム、およびプログラム製品
Document Type and Number:
Japanese Patent JP2010519595
Kind Code:
A
Abstract:
Stitched integrated circuit (IC) chip layout methods, systems and program products are disclosed. In one embodiment, a method includes obtaining from a first entity a circuit design for an IC chip layout that exceeds a size of a photolithography tool field at a second entity, wherein the IC chip layout includes for at least one stitched region of a plurality of stitched regions: a boundary identification identifying a boundary of the at least one stitched region at which stitching occurs and a type indicator indicating whether the at least one stitched region is one of: redundant and unique; dissecting the IC chip layout into stitched regions indicated as unique or redundant at the second entity; and generating a photolithographic reticle at the second entity based on the plurality of stitched regions, the photolithographic reticle having a size that fits within the size of the photolithographic tool field at the second entity.

Inventors:
Dunham, Timothy, Gee
Reidy, Robert, Kay
Ogg, Kevin, N
Russell, Richard, J.
Shamgam, varachi, sea
Application Number:
JP2009551027A
Publication Date:
June 03, 2010
Filing Date:
February 22, 2008
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
G03F1/08; H01L21/027
Domestic Patent References:
JPH10319570A1998-12-04
JP2005037487A2005-02-10
JP2000199973A2000-07-18
JP2004342944A2004-12-02
JP2000171965A2000-06-23
JP2001092108A2001-04-06
JPH0737801A1995-02-07
JPH0645581A1994-02-18
JP2001189254A2001-07-10
JP2002118049A2002-04-19
JPH10319570A1998-12-04
JP2005037487A2005-02-10
JP2000199973A2000-07-18
JP2004342944A2004-12-02
JP2000171965A2000-06-23
JP2001092108A2001-04-06
JPH0737801A1995-02-07
JPH0645581A1994-02-18
Foreign References:
WO2005103827A12005-11-03
Attorney, Agent or Firm:
Takeshi Ueno
Tasaichi Tanae
Yoshihiro City