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Title:
自己訂正する位相デジタル伝達関数を有する位相ロックループ
Document Type and Number:
Japanese Patent JP2011509047
Kind Code:
A
Abstract:
A phase-locked loop includes a phase-to-digital converter portion as well as a novel correction portion. The phase-to-digital converter (PDC) portion outputs a stream of first phase error words. The novel correction portion receives the first phase error words and generates a stream of second phase error words that is supplied to a loop filter. The PDC portion has a phase-to-digital transfer function that exhibits certain imperfections. In a first example, the correction portion determines an average difference between pairs of first phase error words, and uses this average difference to normalize the first phase error words to correct for changes in PDC portion transfer function slope due to changes in delay element propagation delay. In a second example, the correction portion corrects for gain mismatches in PDC portion transfer function. In a third example, the correction portion corrects for offset mismatches in PDC portion transfer function.

Inventors:
Jean, gun
Application Number:
JP2010541499A
Publication Date:
March 17, 2011
Filing Date:
December 24, 2008
Export Citation:
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Assignee:
QUALCOMM INCORPORATED
International Classes:
H03L7/085; H03L7/183
Domestic Patent References:
JP2002204160A2002-07-19
JPH08154053A1996-06-11
JP2006333487A2006-12-07
JPH10322198A1998-12-04
JPH0795055A1995-04-07
JP2001326830A2001-11-22
JP2007259431A2007-10-04
JPH08265140A1996-10-11
JPS62126712A1987-06-09
Foreign References:
US20070075785A12007-04-05
Attorney, Agent or Firm:
Kurata Masatoshi
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Katsumura Hiro
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Takuzo Ichihara
Yamashita Gen