Title:
並列確率的組織化の実施方法
Document Type and Number:
Japanese Patent JP2012503873
Kind Code:
A
Abstract:
A method of positioning at least 2 chips simultaneously on a substrate by parallel stochastic assembly in a first liquid is disclosed. In one aspect, the chips are directed to target sites on the substrate within the first liquid. The target sites are covered with a second liquid. The second liquid and the first liquid are immiscible. The chips are attracting the first liquid. A predetermined surface is chosen or treated on each chip such that it is selectively attracted by the second liquid and attracting the first liquid.
Inventors:
Massimo Maslanieri
Caroline Whelan
Wooter Reitlen
Caroline Whelan
Wooter Reitlen
Application Number:
JP2011528348A
Publication Date:
February 09, 2012
Filing Date:
September 25, 2009
Export Citation:
Assignee:
IMEC
Katholieke Universiteit Leuven,K.U.Leuven R&D
Katholieke Universiteit Leuven,K.U.Leuven R&D
International Classes:
H01L21/60; H01L21/50; H01L21/52
Domestic Patent References:
| JP2008516415A | 2008-05-15 | |||
| JP2007059559A | 2007-03-08 |
Foreign References:
| WO2007037381A1 | 2007-04-05 |
Other References:
JPN7013004589; Ｃ． Ｐ． Ｃｏｌｌｉｅｒ（外７名）: 'Ｅｌｅｃｔｒｏｎｉｃａｌｌｙ ＣｏｎＴｇｕｒａｂｌｅ Ｍｏｌｅｃｕｌａｒ-Ｂａｓｅｄ Ｌｏｇｉｃ Ｇａｔｅｓ' Ｓｃｉｅｎｃｅ ｖｏｌ．２８５, 1999, ｐ．３９１-３９４
Attorney, Agent or Firm:
Takuji Yamada
Mitsuo Tanaka
Mikio Takeuchi
Mitsuo Tanaka
Mikio Takeuchi