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Title:
PCIeアーキテクチャ中でのI/O拡張要求および応答のルーティング
Document Type and Number:
Japanese Patent JP2013527955
Kind Code:
A
Abstract:
A system for implementing non-standard input/output (I/O) adapters in a standardized I/O architecture, comprising an I/O hub communicatively coupled to an I/O bus and a plurality of I/O adapters at I/O adapter addresses, the I/O hub including logic for implementing a method comprising receiving requests from the plurality of I/O adapters, storing the I/O adapter addresses of a requester along with their corresponding target recipient addresses and operation codes, receiving a response from a responder, the response indicating that a request has been completed, determining that the response is in a format other than a format supported by the I/O bus, transforming the response into the format supported by the I/O bus, locating a stored I/O adapter address having a corresponding target recipient address that matches the responder address and a corresponding operation code that matches the responder operation code, and transmitting the response to the stored I/O adapter address.

Inventors:
Greg, Thomas
Cladock, David
Rice, Eric, Norman
Application Number:
JP2013504298A
Publication Date:
July 04, 2013
Filing Date:
June 14, 2011
Export Citation:
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Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
International Classes:
G06F13/36; G06F13/38
Domestic Patent References:
JP2007241526A2007-09-20
JP2007087082A2007-04-05
JP2010134627A2010-06-17
JP2007241526A2007-09-20
JP2007087082A2007-04-05
JP2010134627A2010-06-17
Foreign References:
US20100027559A12010-02-04
US20100027559A12010-02-04
Attorney, Agent or Firm:
Takeshi Ueno
Tasaichi Tanae
Yoshihiro City