Title:
カスタマイズされた占有面積を有する極薄パワートランジスタ及び同期バックコンバータ
Document Type and Number:
Japanese Patent JP2014515189
Kind Code:
A
Abstract:
A power field-effect transistor package is fabricated. A leadframe including a flat plate and a coplanar flat strip spaced from the plate is provided. The plate has a first thickness and the strip has a second thickness smaller than the first thickness. A field-effect power transistor chip having a third thickness is provided. A first and second contact pad on one chip side and a third contact pad on the opposite chip side are created. The first pad is attached to the plate and the second pad to the strip. Terminals are concurrently attached to the plate and the strip so that the terminals are coplanar with the third contact pad. The thickness difference between plate and strip and spaces between chip and terminals is filled with an encapsulation compound having a surface coplanar with the plate and the opposite surface coplanar with the third pad and terminals. The chip, leadframe and terminals are integrated into a package having a thickness equal to the sum of the first and third thicknesses.
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Inventors:
Fan Ray Elbosomer
Osbald Jay Lopez
Jonathan Einokill
Osbald Jay Lopez
Jonathan Einokill
Application Number:
JP2014504075A
Publication Date:
June 26, 2014
Filing Date:
April 09, 2012
Export Citation:
Assignee:
Texas Instruments Japan Ltd.
Texas Instruments Incorporated
Texas Instruments Incorporated
International Classes:
H01L25/07; H01L23/50; H01L25/18
Domestic Patent References:
| JP2004273977A | 2004-09-30 |
Foreign References:
| US20100148346A1 | 2010-06-17 |
Attorney, Agent or Firm:
Kyozo Katayose