Title:
TRANSFER CONTROLLER, PROCESSING SYSTEM AND PROCESSING UNIT
Document Type and Number:
Japanese Patent JP2018156428
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To prevent a problem of change in order of a read request and a write request from arising without providing a circuit for order correction of requests in a transfer path between the transfer path and a memory.SOLUTION: A DMAC (Direct Memory Access Controller) issues S12, after commands for reading and writing one line to a line buffer in a memory are issued S10 to an internal bus (transfer path), a write command for writing a flag to a flag region different from the line buffer. Then a read command for reading the flag region is issued S14 to the internal bus, and it is determined S16 whether a value read out in response matches the flag written at S12. Even if a readout request to the line buffer is received from a host device, no read command is issued to the line buffer until matching is obtained. Once matching is obtained, a return to S10 is made, and read and a write commands to the line buffer are issued.SELECTED DRAWING: Figure 5
Inventors:
NUDESHIMA MASAKI
ONO TOMOYUKI
HASHIMOTO TAKAYUKI
OUE SUGURU
ONO TOMOYUKI
HASHIMOTO TAKAYUKI
OUE SUGURU
Application Number:
JP2017053066A
Publication Date:
October 04, 2018
Filing Date:
March 17, 2017
Export Citation:
Assignee:
FUJI XEROX CO LTD
International Classes:
G06F13/28; G06F12/00
Domestic Patent References:
| JP2005078596A | 2005-03-24 | |||
| JP2016031547A | 2016-03-07 | |||
| JP2008299425A | 2008-12-11 | |||
| JP2005346164A | 2005-12-15 | |||
| JP2010072888A | 2010-04-02 | |||
| JP2006215873A | 2006-08-17 |
Attorney, Agent or Firm:
Patent Corporation yki International Patent Office