Title:
SOLID STATE FAULT CURRENT LIMITER
Document Type and Number:
Japanese Patent JP2019017249
Kind Code:
A
Abstract:
To reduce cost, complexity and size of fault current limiters (FCLs) that prevent a current surge appearing instantaneously when a fault current arises in a system due to any number of events or failures, e.g., power lines or other system components being damaged by severe weather such as lightning strikes.SOLUTION: A solid-state fault current limiter 200 includes a current splitting reactor 202, which comprises a system current input, a passive current output and a control current output. A voltage control reactor 208 includes a first end and a second end, the first end coupled to the control current output, and the second end coupled to the passive current output. A fault current trigger circuit 210 is coupled in parallel with the voltage control reactor and configured to open when a fault current, received by the system current input, exceeds a predefined trigger current. A transient voltage control circuit is further included that is coupled in parallel with the voltage control reactor to receive the fault current.SELECTED DRAWING: Figure 2A
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Inventors:
KASEGN D TEKLETSADIK
CHARLES L STANLEY
SEMAAN FERSAN
PIOTR R LUBICKI
CHARLES L STANLEY
SEMAAN FERSAN
PIOTR R LUBICKI
Application Number:
JP2018181984A
Publication Date:
January 31, 2019
Filing Date:
September 27, 2018
Export Citation:
Assignee:
VARIAN SEMICONDUCTOR EQUIPMENT ASS INC
International Classes:
H02H9/02
Attorney, Agent or Firm:
Kenji Sugimura
Masaaki Ishikawa
Masaaki Ishikawa