Title:
COMPOUND SEMICONDUCTOR WAFER PROCESSING METHOD
Document Type and Number:
Japanese Patent JP2019087642
Kind Code:
A
Abstract:
To provide a compound semiconductor wafer processing method capable of thinning the wafer without generating processing distortion.SOLUTION: A compound semiconductor wafer processing method of processing a wafer 11 formed of a compound semiconductor obtained by ionically bonding a first atom that is a semiconductor element and a second atom that is an element different from the first atom, includes: etching a surface of the wafer 11 by high-density plasma generated from an etching gas reacting with the first atom; and removing a remaining particle layer 12 containing the second atom on the surface of the wafer 11 after the etching by mechanical polishing.SELECTED DRAWING: Figure 2
Inventors:
YAMADA HIROSHI
Application Number:
JP2017214861A
Publication Date:
June 06, 2019
Filing Date:
November 07, 2017
Export Citation:
Assignee:
HIGHCHIC CO LTD
International Classes:
H01L21/3065; H01L21/304
Domestic Patent References:
| JP2013077644A | 2013-04-25 | |||
| JP2011176243A | 2011-09-08 | |||
| JP2015179830A | 2015-10-08 | |||
| JPS57124438A | 1982-08-03 | |||
| JP2006032655A | 2006-02-02 | |||
| JPS62216335A | 1987-09-22 | |||
| JP5103025B2 | 2012-12-19 |
Foreign References:
| WO2015093406A1 | 2015-06-25 |
Attorney, Agent or Firm:
Hisashi Kato
Keita Tohsaka
Toru Minase
Keita Tohsaka
Toru Minase