Title:
MEMORY SYSTEM AND CONTROL METHOD
Document Type and Number:
Japanese Patent JP2019105873
Kind Code:
A
Abstract:
To realize a memory system that can increase the number of write destination blocks being available at the same time.SOLUTION: A memory system receives from a host a write request including a first identifier associated with one write destination block and storage position information indicating a position in a write buffer on a memory of the host in which memory first data to write is stored. When the first data is written in a nonvolatile memory, the memory system acquires the first data from the write buffer by sending out a transfer request including the storage position information to the host, transfers the first data to the nonvolatile memory, and writes the first data in the one write destination block.SELECTED DRAWING: Figure 6
Inventors:
SUGANO SHINICHI
YOSHIDA HIDEKI
YOSHIDA HIDEKI
Application Number:
JP2017236269A
Publication Date:
June 27, 2019
Filing Date:
December 08, 2017
Export Citation:
Assignee:
TOSHIBA MEMORY CORP
International Classes:
G06F13/14; G06F13/10
Domestic Patent References:
| JP2017162068A | 2017-09-14 | |||
| JP2017054465A | 2017-03-16 | |||
| JP2013109419A | 2013-06-06 |
Foreign References:
| US20170123721A1 | 2017-05-04 | |||
| WO2016194162A1 | 2016-12-08 | |||
| US20160321010A1 | 2016-11-03 |
Attorney, Agent or Firm:
Suzue International Patent Office