Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2019121735
Kind Code:
A
Abstract:
To provide a semiconductor device that is able to hinder an increase in emitter resistance and is suitable for a high output operation.SOLUTION: A plurality of unit transistors are arranged side by side on a surface of a substrate in a first direction. Input capacitance elements are arranged in correspondence with the unit transistors. An emitter common wire is connected to an emitter layer of each unit transistor. In a position overlapping the emitter common wire, a veer hole reaching from the emitter common wire to a rear surface of the substrate is provided. A collector common wire is connected to a collector layer of each unit transistor. The plurality of input capacitance elements, each emitter common wire, the plurality of unit transistors, and each collector common wire are arranged in that order in a second direction. A base wire connecting the plurality of input capacitance elements and a base layer of a corresponding unit transistor intersects the emitter common wire without physical contact therewith.SELECTED DRAWING: Figure 1
Inventors:
KOYA SHIGEKI
TSUTSUI TAKAYUKI
NAKAI KAZUTO
TANAKA YUSUKE
TSUTSUI TAKAYUKI
NAKAI KAZUTO
TANAKA YUSUKE
Application Number:
JP2018002030A
Publication Date:
July 22, 2019
Filing Date:
January 10, 2018
Export Citation:
Assignee:
MURATA MANUFACTURING CO
International Classes:
H01L21/8222; H01L21/331; H01L21/768; H01L21/822; H01L23/522; H01L27/04; H01L27/06; H01L29/737
Attorney, Agent or Firm:
Mikio Kuruyama
Manabu Kawamoto
Manabu Kawamoto