Title:
INTERNAL VOLTAGE GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JP2019154092
Kind Code:
A
Abstract:
To improve a noise suppression function.SOLUTION: An internal voltage generating circuit comprises negative voltage generating circuits (P and N). The negative voltage generating circuits (P and N) are connected in parallel, and a drive signal is inputted to a charge pump circuit (22) at opposite phases from a signal drive circuit (21). A plurality of pairs of negative voltage generating circuits (P and N) are disposed, and are arranged in adjacent positions.SELECTED DRAWING: Figure 1
Inventors:
AOKI EIJI
MORIKAWA YOSHINAO
MORIKAWA YOSHINAO
Application Number:
JP2018035709A
Publication Date:
September 12, 2019
Filing Date:
February 28, 2018
Export Citation:
Assignee:
SHARP KK
International Classes:
H02M3/07
Domestic Patent References:
| JP2002032987A | 2002-01-31 | |||
| JP2010539627A | 2010-12-16 |
Foreign References:
| US20140035661A1 | 2014-02-06 | |||
| US20060220728A1 | 2006-10-05 | |||
| US20020008566A1 | 2002-01-24 | |||
| US20090073795A1 | 2009-03-19 |
Attorney, Agent or Firm:
Harakenzo world patent & trademark