Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP2019169510
Kind Code:
A
Abstract:
To reduce the chip area of a semiconductor memory.SOLUTION: A semiconductor memory according to an embodiment includes a plurality of first electric conductors, a plurality of first pillars MP, and a pillar array. The plurality of first electric conductors are stacked with insulators interposed. The plurality of first pillars MP pass through the plurality of first electric conductors respectively, and parts of intersection with the plurality of first electric conductors function as memory cells, respectively. The pillar array includes a plurality of second pillars RP arranged in a first direction, and includes a first array of second pillars RP and a second array of second pillars RP. The first array of second pillars RP and the second array of second pillars RP are arranged in a second direction crossing the first direction. First pillars MP are arranged on both second-directional sides of the second pillars RP. The first electric conductors are provided successively on both the second-directional sides of the second pillars RP included in the pillar array, and also provided successively in the second direction between the first array of second pillars RP and the second array of second pillars RP.SELECTED DRAWING: Figure 8
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Inventors:
FUJII KOTARO
SONODA MASAHISA
KITO TAKASHI
NAGASHIMA MASASHI
KOBAYASHI SHIGEKI
SONODA MASAHISA
KITO TAKASHI
NAGASHIMA MASASHI
KOBAYASHI SHIGEKI
Application Number:
JP2018054147A
Publication Date:
October 03, 2019
Filing Date:
March 22, 2018
Export Citation:
Assignee:
TOSHIBA MEMORY CORP
International Classes:
H01L27/11582; G11C11/56; G11C16/04; G11C16/14; H01L21/336; H01L27/11565; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Kurata Masatoshi
Nobuhisa Nogawa
Takashi Mine
Naoki Kono
Ukai Ken
Nobuhisa Nogawa
Takashi Mine
Naoki Kono
Ukai Ken