Title:
SCHEDULING METHOD AND SCHEDULING APPARATUS
Document Type and Number:
Japanese Patent JP2019179417
Kind Code:
A
Abstract:
To use efficiently a cache memory even when many processes are being performed in parallel.SOLUTION: A scheduling apparatus comprises: a tag reference unit (141) for reading tag information that indicates the contents of memory access to a memory used for each of a plurality of operations in a processing node; and an allocation unit (142) for determining a processing order for the plurality of operations based on the tag information.SELECTED DRAWING: Figure 5
Inventors:
KURI MASAFUMI
SUGIMOTO HIDEKI
SUGIMOTO HIDEKI
Application Number:
JP2018068434A
Publication Date:
October 17, 2019
Filing Date:
March 30, 2018
Export Citation:
Assignee:
DENSO CORP
NSITEXE INC
NSITEXE INC
International Classes:
G06F9/48; G06F8/41
Domestic Patent References:
| JPH10116198A | 1998-05-06 | |||
| JPH0844577A | 1996-02-16 |
Attorney, Agent or Firm:
Toru Kamada
Takuma Tsuda
Takuma Tsuda