Title:
PARALLEL PROCESSOR, REDUCTION OPERATION SYSTEM, AND REDUCTION OPERATION METHOD
Document Type and Number:
Japanese Patent JP2020013336
Kind Code:
A
Abstract:
To provide a parallel processor, a reduction operation system, and a reduction operation method that improve communication reliability.SOLUTION: A plurality of distribution nodes 10 exist. Each distribution node 10 obtains discrete logarithm data, which is a discrete logarithm of transmission data, and transmits the obtained discrete logarithm data. A reduction device 20 calculates a sum of the discrete logarithm data transmitted by each distribution node 10. Further, the reduction device 20 transmits the calculated sum to an aggregation node 30. The aggregation node 30 decodes the sum of the discrete logarithm data transmitted by the reduction device 20, and acquires each transmission data.SELECTED DRAWING: Figure 1
Inventors:
ISHII KUNINORI
USUI TETSUZO
HASHIMOTO TAKESHI
USUI TETSUZO
HASHIMOTO TAKESHI
Application Number:
JP2018135138A
Publication Date:
January 23, 2020
Filing Date:
July 18, 2018
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G06F13/00; G06F11/07; G06F11/30; H03M7/30
Domestic Patent References:
| JP2015233178A | 2015-12-24 | |||
| JP2010165275A | 2010-07-29 | |||
| JP2010122246A | 2010-06-03 | |||
| JP2013192129A | 2013-09-26 |
Attorney, Agent or Firm:
Sakai International Patent Office