Title:
SYSTEM AND METHOD FOR RETAINING DRAM DATA WHEN REPROGRAMMING RECONFIGURABLE DEVICES BY USING DRAM MEMORY CONTROLLERS INCORPORATING DATA MAINTENANCE BLOCK COLLOCATED WITH MEMORY MODULE OR SUBSYSTEM
Document Type and Number:
Japanese Patent JP2020166874
Kind Code:
A
Abstract:
To provide a system and a method for retaining dynamic random access memory (DRAM) data when reprogramming reconfigurable devices by using DRAM memory controllers such as field programmable gate arrays (FPGAs).SOLUTION: A DRAM memory controller is used in conjunction with a data maintenance block collocated with a DRAM memory 102 and coupled to an I2C interface of a reconfigurable logic device. The FPGA drives the majority of DRAM input/output (I/O). The data maintenance block drives self-refresh command inputs. Even though the FPGA reconfigures and the majority of the DRAM inputs are tri-stated, the data maintenance block provides stable input levels on the self-refresh command inputs.SELECTED DRAWING: Figure 1
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Inventors:
TIMOTHY J TEWALT
Application Number:
JP2020094201A
Publication Date:
October 08, 2020
Filing Date:
May 29, 2020
Export Citation:
Assignee:
SRC LABS LLC
International Classes:
G06F12/00; G06F11/14; G11C11/406
Domestic Patent References:
| JP2006350859A | 2006-12-28 | |||
| JP2010262645A | 2010-11-18 | |||
| JP2001265647A | 2001-09-28 |
Foreign References:
| WO2010137330A1 | 2010-12-02 | |||
| US6119200A | 2000-09-12 |
Attorney, Agent or Firm:
Longhua International Patent Service Corporation