Title:
DISPLAY LIGHTING METHOD AND DISPLAY
Document Type and Number:
Japanese Patent JP2020183971
Kind Code:
A
Abstract:
To provide a display lighting method in which variation in image quality or luminance is suppressed even in a long-term use without adding a complicated circuit structure.SOLUTION: A display lighting method includes a step (A) of applying voltage based on display image data to a gate electrode of a vertical organic light-emitting transistor, and a step (B) of, after the step (A), applying voltage to a gate electrode of the vertical organic light-emitting transistor, the voltage being positive or negative voltage opposite to the voltage applied to the gate electrode of the vertical organic light-emitting transistor in the step (A) on the basis of a value of the voltage applied to a source electrode of the vertical organic light-emitting transistor.SELECTED DRAWING: Figure 1
Inventors:
KATSUI HIROMITSU
Application Number:
JP2019086610A
Publication Date:
November 12, 2020
Filing Date:
April 26, 2019
Export Citation:
Assignee:
JSR CORP
International Classes:
G09G3/3233; G09F9/30; G09G3/20; G09G3/3266; G09G3/3275; H01L21/28; H01L27/32; H01L29/417; H01L29/423; H01L29/47; H01L29/49; H01L29/786; H01L29/872; H01L51/00; H01L51/30; H01L51/50
Domestic Patent References:
| JP2014505324A | 2014-02-27 |
Foreign References:
| WO2010146707A1 | 2010-12-23 | |||
| US20180358568A1 | 2018-12-13 |
Attorney, Agent or Firm:
Patent Business Corporation Unias International Patent Office