Title:
OPERATIONAL AMPLIFIER
Document Type and Number:
Japanese Patent JP2021132357
Kind Code:
A
Abstract:
To correct an input offset voltage over a wide voltage range.SOLUTION: A PMOS input differential pair 10 is connected to an inverting input terminal INN and a non-inverting input terminal INP. An NMOS input differential pair 12 is connected to the inverting input terminal INN and the non-inverting input terminal INP. An output stage 20 receives the outputs of the PMOS input differential pair 10 and the NMOS input differential pair 12. A first correction circuit 40 corrects an offset voltage of the PMOS input differential pair 10. A second correction circuit 70 corrects an offset voltage of the NMOS input differential pair 12. The first correction circuit 40 and the second correction circuit 70 are configured to operate over an operating region of the PMOS input differential pair 10, an operating region of the NMOS input differential pair 12, and a transition region in which both of them operate.SELECTED DRAWING: Figure 3
Inventors:
NOMURA HISAHIRO
MANABE TAKATOSHI
MANABE TAKATOSHI
Application Number:
JP2020028195A
Publication Date:
September 09, 2021
Filing Date:
February 21, 2020
Export Citation:
Assignee:
ROHM CO LTD
International Classes:
H03F3/34; H03F3/45; H03F3/68
Domestic Patent References:
| JPH08204468A | 1996-08-09 | |||
| JP2010041131A | 2010-02-18 | |||
| JP2014204291A | 2014-10-27 | |||
| JPH08237051A | 1996-09-13 |
Attorney, Agent or Firm:
Sakaki Morishita
Masaki Taiki
Masaki Taiki