Title:
DISPLAY DEVICE
Document Type and Number:
Japanese Patent JP2021141331
Kind Code:
A
Abstract:
To suppress deterioration of the electric characteristics of a transistor having an oxide semiconductor layer or of a semiconductor device comprising the transistor.SOLUTION: A silicon layer is provided in a transistor using an oxide semiconductor as a channel layer so as to be in contact with a surface of the oxide semiconductor layer. The silicon layer is provided so as to be in contact with at least a region of the oxide semiconductor layer in which a channel is formed. A source electrode layer and a drain electrode layer are provided in a region of the oxide semiconductor layer in which the silicon layer is not provided.SELECTED DRAWING: Figure 1
Inventors:
SAKATA JUNICHIRO
GOTO HIROMITSU
SHIMAZU TAKASHI
GOTO HIROMITSU
SHIMAZU TAKASHI
Application Number:
JP2021073860A
Publication Date:
September 16, 2021
Filing Date:
April 26, 2021
Export Citation:
Assignee:
SEMICONDUCTOR ENERGY LAB CO LTD
International Classes:
H01L29/786; G09F9/30; H01L21/336; H01L27/32; H01L51/50; H05B33/14
Domestic Patent References:
| JP2008205469A | 2008-09-04 | |||
| JP2008140984A | 2008-06-19 | |||
| JP2009272427A | 2009-11-19 | |||
| JP2007073559A | 2007-03-22 | |||
| JP2007096055A | 2007-04-12 | |||
| JP2005285890A | 2005-10-13 | |||
| JP2007250983A | 2007-09-27 |